Fabrication of ultra large scale integrated circuits on a silicon semiconductor wafer involves the covering of thin film devices with a dielectric layer prior to deposition of metal. This dielectric layer may be referred to as the pre-metal dielectric layer. One of the important features of this layer is good planarity of the surface that it creates. Otherwise, it can cause depth of focus issue for a subsequent photolithography process and high contact resistance. One approach to achieve the planarity is to use a dielectric material that is flowable at elevated temperature. Thus a planar surface can be achieved by reflow at an elevated temperature after dielectric material deposition. Boron-phosphate-silicate-glass (BPSG) is typically used as the dielectric material. The BPSG material is a compound of silicon oxide with boron and phosphorus. Following deposition of the BPSG pre-metal dielectric layer, high aspect ratio openings are formed in the layer to expose portions of the underlying silicon wafer to which electrical contact is to be established. However, a native oxide layer may formed on top of Si surface after the contact holes are formed. In order to ensure good electrical contact, this native oxide needs to be removed. A wet clean step, normally referred as HF dip, is normally used as the conventional method for this native oxide removal process. However, as the feature size shrinks, a wet clean step cannot be used due to: 1. High BPSG/SiO2 selectivity, which results in a large change in critical dimension (CD); 2. The wet chemical may not penetrate to the bottom of the smaller features; and, 3. Environmental concerns for the wet chemical clean. Thus a dry clean (plasma etch) method is preferred for the native oxide removal step. The electrical contact is then formed by first performing a pre-metallization step in which a metal silicide is formed on the exposed silicon surface at the bottom of each opening. Each opening is then filled with metal.
The plasma etch process is performed in an etch reactor chamber and may employ a remote plasma source using a process gas containing hydrogen and fluorine compounds. Following the plasma etch clean process, the wafer is transferred from the etch chamber to a metallization reactor chamber. During this transfer, the wafer may be exposed for significant periods to an atmospheric environment. It has been observed that during this exposure, convex-shaped defects, which may possibly consist of BPO4 or BPO4.3H2O, begin to form on the surface of the BPSG dielectric layer, and grow in size from a few nanometer to several tens of microns, in some cases. These convex-shaped surface defects adversely affect the electrical behavior of contacts formed in the openings and can interfere with photolithographic steps. Attempts have been made to alter the parameters of the various process steps described above in an attempt to prevent formation of these defects, but such attempts have been unsuccessful.